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On Mon, 15 Nov 2004, Chris Wilkson wrote:
> Those are master-slave flipflops. If you look at the F1 cell, there are
> 2 s-r latches there. At no time are both those latches open. The first
> one (driven by the nor gates) is open only when clock is low. The second
> one is open only when clock is high.
Ok, I see it now. What am I doing wrong here then?
entity bb_boxf1 is
port (
clock : in std_logic;
q : out std_logic;
notq : out std_logic;
reset : in std_logic;
notr : in std_logic;
nots : in std_logic);
end bb_boxf1;
architecture behavioral of bb_boxf1 is
signal tmp1 : std_logic;
signal tmp2 : std_logic;
signal tmp3 : std_logic;
signal tmp4 : std_logic;
signal tmp5 : std_logic;
signal tmp6 : std_logic;
signal tmp7 : std_logic;
signal tmp8 : std_logic;
begin
tmp1 <= not (clock or nots);
tmp2 <= not (clock or notr);
tmp3 <= not (tmp1 or tmp4);
tmp4 <= not (tmp2 or reset or tmp3);
tmp5 <= clock and tmp3;
tmp6 <= clock and tmp4;
tmp7 <= not (tmp5 or reset or tmp8);
tmp8 <= not (tmp7 or tmp6);
q <= tmp7;
notq <= tmp8;
end behavioral;
Do I need to rewrite this to be a little more straightforward?
Maybe more like this (untest code ahead, may contain syntax errors...)
architecture behavioral of bb_boxf1 is
signal tmp1 : std_logic;
signal tmp2 : std_logic;
begin
procedure (clock)
begin
if (clock'event and clock = '0') then
if (nots = '0') then
tmp1 <= '1';
elsif (notr = '0') then
tmp1 <= '0';
end if;
end if;
end procedure;
procedure (clock)
begin
if (clock'event and clock = '1') then
if (reset = '1') then
tmp2 <= '0';
else
tmp2 <= tmp1;
end if;
end if;
end procedure;
q <= tmp2;
notq <= not tmp2;
end behavioral;
- --
adam@xxxxxxxxxxxxxxxx http://cuddlepuddle.org/~adam
KG6GZR http://cuddlepuddle.org/~adam/resume.html
"Feminist? Why would I want to alienate half the population? I'm an egalitarian."
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