Re: [stella] TIA video timing

Subject: Re: [stella] TIA video timing
From: Chris Wilkson <ecwilkso@xxxxxxx>
Date: Thu, 10 Mar 2005 01:53:09 -0500
Errrrmmm...no.

sync should be 16 cycles wide, not 68.  blank should be 68 cycles wide.
I don't remember the *exact* relative timing at the moment, but I think it's
like this:

begin hblank (wait 16 cycles)
begin hsync (wait 16 cycles)
end hsync (wait 36 cycles)
begin active video (wait 160 cycles)

The /sync pin is hsync xnor vsync, like you have it below.
The /blank pin is hblank nor vblank.
Both pins are active low.

Clever use of overflow to get weird counts like 68, btw.
The counts above work well with this scheme...it's why they
chose the numbers they did.  Cheap as possible!!!

-Chris

On Thu, 10 Mar 2005, Adam Wozniak wrote:

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> I've been scratching my head here for a while, and I'm still not
> certain I've got this right.  Can someone give me a yea or nay on this?
>
> - -- posNOW is a 8 bit counter, that goes up from 0 to 227
> - -- regVSYNC is bit 1 of TIA register address VSYNC
> - -- regVBLANK(0) is bit 1 of TIA register address VBLANK
> - -- sync is the sync output pin of the TIA (pin 2)
> - -- nblk is the bl output pin of the TIA (pin 6)
>
> - -- video sync output
> process (posNOW)
> begin
>    if posNOW = "11100000" then        -- 11100000 == 224
>       sync <= not ('1' xor regVSYNC);
>    elsif posNOW = "01000000" then     -- 01000000 == 64
>       sync <= not ('0' xor regVSYNC);
>    end if;
> end process;
>
> - -- video blank output
> process (regVBLANK)
> begin
>    nblk <= not regVBLANK(0);
> end process;
>
>
> Once I'm sure I've got this right, I can move into testing.
>
> - --
> adam@xxxxxxxxxxxxxxxx        http://cuddlepuddle.org/~adam
> KG6GZR                       http://cuddlepuddle.org/~adam/resume.html
>
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