On Thu, 10 Mar 2005, Adam Wozniak wrote:
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> On Thu, 10 Mar 2005, Chris Wilkson wrote:
> > Errrrmmm...no.
> >
> > sync should be 16 cycles wide, not 68. blank should be 68 cycles wide.
> > I don't remember the *exact* relative timing at the moment, but I think it's
> > like this:
> >
> > begin hblank (wait 16 cycles)
> > begin hsync (wait 16 cycles)
> > end hsync (wait 36 cycles)
> > begin active video (wait 160 cycles)
>
> This may be a better reference:
> http://www.cuddlepuddle.org/~adam/fpga2600/TIA_HW_Notes.txt
>
> It shows them setting hsync at 16 and clearing it at 32.
> It shows them setting hblank at 224 and clearing it at 64.
I can't check the hardware right now, but this should work. NTSC isn't too
picky. I did check my notes and it shows only 16 cycles between hblank
and hsync. I know my gerenated hardware's timing signals were identical
to a real TIA's, but I don't know if that hardware matches these notes.
> > The /sync pin is hsync xnor vsync, like you have it below.
> > The /blank pin is hblank nor vblank.
> > Both pins are active low.
>
> So now I'm thinking:
>
> -- posNOW is a 8 bit counter, that goes up from 0 to 227
> -- regVSYNC is bit 1 of TIA register address VSYNC
> -- regVBLANK(0) is bit 1 of TIA register address VBLANK
> -- sync is the sync output pin of the TIA (pin 2)
> -- nblk is the bl output pin of the TIA (pin 6)
>
> -- video sync output
> process (posNOW)
> begin
> if posNOW = "00010000" then -- 00010000 == 16
> sync <= not ('1' xor regVSYNC);
> elsif posNOW = "00100000" then -- 00100000 == 32
> sync <= not ('0' xor regVSYNC);
> end if;
> end process;
>
> -- video blank output
> process (regVBLANK)
> begin
> if posNOW = "11100000" then -- 11100000 == 224
> nblk <= not ('1' or regVBLANK(0));
> elsif posNOW = "01000000" then -- 01000000 == 64
> nblk <= not ('0' or regVBLANK(0));
> end if;
> end process;
>
>
> Did I get the logic levels right? Ack, I still don't feel
> like I'm on solid ground here.
When regVSYNC is a one, you want the pin to be high during hsync and low otherwise.
So you need to invert your counter logic:
sync <= ('0' xor regVSYNC); -- turn on hsync
sync <= ('1' xor regVSYNC); -- turn off hsync
I think the nblk logic is ok. But you should leave the ability to shift the hblank
pulse 4 cycles to the right, just in case the numbers you're using are wrong. This
should be easy to with the given code, but I don't know what other timing signals you
are depending on hblank for. It should work either way, it'll just look a little
different on a real TV.
I assume you have an o'scope for this project? (If not, then *GET* one!!!)
Just measure the number of PHI0 clocks between the falling edge of /BLK (pin 6) and
/SYNC (pin 2) of a real TIA. You should of course do this while VBLANK and VSYNC
are turned off, ie. during an active scanline.
-Chris
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