Subject: [stella] Ball vertical delay From: Adam Wozniak <adam@xxxxxxxxxxxxxxxx> Date: Wed, 8 Jun 2005 01:04:23 -0400 |
-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 In the TIA manual, it says... % A second graphics (enable) bit is alternately loaded from the output of % the first, one line after the first was loaded from the data bus. A ball % vertical delay bit (VDELBL) selects which of these two graphics bits is % used for the ball serial output. The first graphics bit (ENABL) should % be loaded during the same horizontal blank time as player 0 (GRP0), % because GRP1 is used to load the second enable bit from the output of % the first on alternate lines. Can someone rephrase this for me? I don't understand it as worded here, and I think I got it wrong in my VHDL. case a is [...] when "011011" => regGRP0a <= d; -- load the GRP0 main register regGRP1b <= d; -- load the GRP1 delay register when "011100" => regGRP1a <= d; -- load the GRP1 main register regGRP0b <= d; -- load the GRP0 delay register [...] when "011111" => regENABLa <= d(1); -- load the ENABL main register regENABLb <= regENABLa; -- load the ENABL delay register ??? [...] end case; I know this is wrong, but I'm not sure what the right thing is. Or maybe the delayed ENABL should be loaded somewhere completely different? - -- adam@xxxxxxxxxxxxxxxx http://cuddlepuddle.org/~adam KG6GZR http://cuddlepuddle.org/~adam/resume.html -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.2.1 (GNU/Linux) iD4DBQFCpnv3yvXf5Z0z5zERAvxJAJj0DafK+Rv4caWg0cFU9eSY5W7VAKCIjvux 4buBCgTSnakarmMMSFeFKg== =3yMb -----END PGP SIGNATURE----- Archives (includes files) at http://www.biglist.com/lists/stella/archives/ Unsub & more at http://stella.biglist.com
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