Re: [stella] 8K Cart question

[Chad Schell <gamer@xxxxxxxxxxx>]

Mark,

Here's my F6 bankswitching VHDL code.  Since I'm currently working on a 
breadboard it's also my F8 code, just tie A13 on the eprom to ground.  It's 
for a Xilinx XC9536/72 -15.  All the  "clks" are my simple digital delay 
method.  All the keep statements to stop the VHDL compiler from optimizing 
away my delay.

I welcome any comments or improvements to this code.  Anyone is welcome to 
use it for their own private, non-commercial ventures.

================Code Below===================================

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.numeric_std.ALL;

entity atari is
    Port (
                addr_in : in std_logic_vector(12 downto 0);
                oe : out std_logic;
        a12 : out std_logic;
        a13 : out std_logic
        );
end atari;

architecture behavioral of atari is
signal glitch : std_logic_vector(12 downto 0);
signal clk1 : std_logic;
signal clk2 : std_logic;
signal clk : std_logic;
signal clk3 : std_logic;
signal clk4 : std_logic;
signal clk5 : std_logic;
signal clk6 : std_logic;
signal clk7 : std_logic;
attribute KEEP : string;
attribute KEEP of clk1 : signal is "TRUE";
attribute KEEP of clk2 : signal is "TRUE";
attribute KEEP of clk3 : signal is "TRUE";
attribute KEEP of clk4 : signal is "TRUE";
attribute KEEP of clk5 : signal is "TRUE";
attribute KEEP of clk6 : signal is "TRUE";
attribute KEEP of clk7 : signal is "TRUE";
attribute KEEP of clk : signal is "TRUE";
begin

        oe <= not addr_in(12);

        clk1 <= not clk;
        clk2 <= not clk1;
        clk3 <= not clk2;
        clk4 <= not clk3;
        clk5 <= not clk4;
        clk6 <= not clk5;

        clk7 <= clk and (not clk1) and clk2 and
                (not clk3) and clk4 and (not clk5) and clk6;

        bank_switch_g: process(addr_in, glitch)
        begin
                if glitch /= addr_in then
                        glitch <= addr_in;
                        clk <= '0';
                else
                        clk <= '1';
                end if;
        end process;

        bank_switch: process(clk7,addr_in)
        begin
                if rising_edge(clk7) then
                        if addr_in = X"1FF6" then
                                a12 <= '0';
                                a13 <= '0';
                        elsif addr_in = X"1FF7" then
                                a12 <= '1';
                                a13 <= '0';
                        elsif addr_in = X"1FF8" then
                                a12 <= '0';
                                a13 <= '1';
                        elsif addr_in = X"1FF9" then
                                a12 <= '1';
                                a13 <= '1';
                        end if;
                end if;
        end process;
end behavioral;
--Copyright 2000 Chad Schell

============================================
Chad Schell
gamer@xxxxxxxxxxx
Like the Intellivision?  Check out the Intellicart.
http://www.schells.com/intellicart.shtml


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