Hi all,
I'm not actually certain how to go about providing a debugger. Wouldn't a
full debugger require support in the hardware to let you read all registers
at any point without changing them? I know some debuggers are implemented
as basically ISRs, relying on the fact that the processor always completes
at least one instruction between ISRs. Thus using a constantly triggered
ISR one can cause the processor to single step through the code. Does the
6502C do this?
The best idea I've heard so far is to just let people use the SRAM and map
whatever, wherever they want to. The SRAM doesn't have to be fixed at any
point, and with 512kB there is room for people to write fairly large games
and still install debugging routines.
However, if someone wants to clue me in on specific ways to do these
things, please feel free. Creating debuggers is definitely not my area of
expertise.
Lists:
# Bankswitching Formats Tested:
* 2600: 2K,4K,F8,F8SC,F6,F6SC,F4,F4SC,Megaboy,Commavid,E0,E7,FE,FA,3F
Why isn't FASC listed here (suspect that's just oversight)?
FASC?? Do you mean FA with extra RAM? That's actually the standard for
FA, and it has twice the RAM as provided by the Superchip (SC). For the
Cuttle Cart I named FA without ram FANR. There are no games that use it to
my knowledge, but it would trivial to implement.
How about 3F+ (3F, except 256 (or whatever your limit is) banks instead
of just 4 banks) and the MC as supported by the "stella" emulator?
Extending 3F to larger size is no problem. What is MC?
I understand not supporting Pitfall II's sound. Is it possible to
support only the extra graphics?
I don't know. I've never really bothered to figure out how Pitfall II
works. I can't bring myself to sift through the patent.
Can anyone point me to a very simple, summarized description of what's
needed? My impression is that much of what's talked about in the patent
isn't actually used.
Chad
============================================
Chad Schell
http://www.schells.com/
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