Re: [Fpga2600] TIA schematic question

Subject: Re: [Fpga2600] TIA schematic question
From: Adam Wozniak <adam@xxxxxxxxxxxxxxxx>
Date: Mon, 15 Nov 2004 08:29:59 -0800 (PST)
Hash: SHA1

On Mon, 15 Nov 2004, Eric Crabill wrote:
> > There are two boxes labelled F1, which appear
> > to be S/R latches with inverted inputs
> They are actually S/R flip flops, and are edge
> triggered (unlike most of the other D/L components
> on the schematics, which are latches...)
> > As near as I can tell, and by looking at
> > simulations, they are configured in an
> > unstable manner.  How is this resolved?
> If they were latches, the oscillations you
> describe would certainly take place.  But
> since they are flip flops, the "next state"
> is only updated on the rising edge of the
> clock.  It's a 2-bit counter.  You can
> compare your result against my "behavioral"
> description of this at:

The F1 box is detailed on page 1, section C1.  I don't see anything
there that would prevent those oscillations from happening.  Indeed,
my VHDL follows the diagram precisely, and the oscillations DO occur
in the simulation.

> Maybe someone else can confirm, but I do believe
> portions of this design use dynamic logic and
> are dependant on propogation delays / capacitance
> of various nodes.  Every place you see a (*) on
> the schematic...

Those I've taken care of with D latches.

- -- 

"Feminist?  Why would I want to alienate half the population?  I'm an egalitarian."

Version: GnuPG v1.2.1 (GNU/Linux)


Current Thread