-----Original Message-----
From: Adam Wozniak <adam@xxxxxxxxxxxxxxxx>
Sent: Jun 17, 2005 1:32 PM
To: stella@xxxxxxxxxxxxxxxxxx
Subject: Re: [stella] Clock skew...
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
On Fri, 17 Jun 2005, C. Bond wrote:
> According to the docs I have, the time lag (delay) between
> the CPU phase 0 clock, generated by the TIA, and the CPU
> phase 2 clock, generated by the 6507, may be as much as
> 150nsec. This seems excessive. Has anyone ever measured the
> difference? I would appreciate any input from someone with
> other information or the ability to 'scope the hardware.
[Adam]
It is excessive.
I measured it a long while back, and was surprised at how close
phi0 and phi2 really were. Unfortunately my memory isn't perfect,
but I seem to recall a number closer to 15ns than 150ns.
[C. Bond]
Since phi2 can be generated (and meet the non-overlapping of phi1 and phi2 spec) by
simply using an inverter and a NOR latch (+ bus driver), I would expect the delay to
be short.
[Adam]
I'll see if I can remember to measure it after work tonight.
[C. Bond]
Thanks for your help.
- --
adam@xxxxxxxxxxxxxxxx http://cuddlepuddle.org/~adam
KG6GZR http://cuddlepuddle.org/~adam/resume.html
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.2.1 (GNU/Linux)
iD8DBQFCszL+yvXf5Z0z5zERApFMAJ9hgbMZogix9J3lbHhjPMeaPXyk6wCaAj7w
oDDRD0dXc/LU4goV5vOCwwA=
=DTCr
-----END PGP SIGNATURE-----
Archives (includes files) at http://www.biglist.com/lists/stella/archives/
Unsub & more at http://stella.biglist.com
Archives (includes files) at http://www.biglist.com/lists/stella/archives/
Unsub & more at http://stella.biglist.com
