That's an interesting schematic. Since the FET's are n-channel (NMOS),
they must act like a switch that's on when the gate goes high. When it goes
low, the output voltage probably stays preserved at the current state for a
little while, because of gate capacitance. Since all the gates are driven by
H01 and H02, I can assume these are oscillating signals (Horizontal clocks
of some kind), so they never stay low for too long.
So, I guess you think of the FET's as D-type flip-flops as long as they get
clocked often enough. (You probably wouldn't want to duplicate the logic
this way, but you could.)
FWIW, I think the astrocade custom chips use this same kind of technique.
You can see the bare FET's in their patents.
I haven't been following this thread very carefully - have these schematics
been posted anywhere yet? Are they going to be? Pretty please? :)
Thanks,
-Frank
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