----- Original Message -----
From: "Frank Palazzolo" <palazzol@xxxxxxxx>
> That's an interesting schematic. Since the FET's are n-channel (NMOS),
> they must act like a switch that's on when the gate goes high. When it
goes
> low, the output voltage probably stays preserved at the current state for
a
> little while, because of gate capacitance. Since all the gates are driven
by
> H01 and H02, I can assume these are oscillating signals (Horizontal clocks
> of some kind), so they never stay low for too long.
>
> So, I guess you think of the FET's as D-type flip-flops as long as they
get
> clocked often enough. (You probably wouldn't want to duplicate the logic
> this way, but you could.)
This is a very interesting idea. I would not have thought of it in a
million years.
> I haven't been following this thread very carefully - have these
schematics
> been posted anywhere yet? Are they going to be? Pretty please? :)
They are very big drawings and would take a long time to scan in. But I
have posted two scans here:
http://www.whimsey.com/tia/HCLOCK1.GIF
http://www.whimsey.com/tia/HCLOCK2.GIF
Just to tease you. ;-) Actually if somebody else wants to take on the
project of scanning and posting that's O.K. with me. If I'm doing it, it
will probably happen a little at a time, and the scans probably won't stay
up permanantly. Note that these .GIF's don't display properly in Opera or
Internet Explorer. Netscape 6.1 displays them properly. But I would
recommend downloading them and viewing them in something else. I use
IrfanView for things like this. This way you can scale the scan to fit your
screen.
In any case, the two scans that I've posted show how the H01 and H02 signals
are generated. I'd be curious to know if somebody could tell me what they
think the waveforms of H01 & H02 would look like. Are they square waves?
How does the phase relate to the input? What kind of propagation delay has
been introduced by the rather elaborate circuit used to generate them?
Thanks,
John
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