At 03:56 PM 8/29/2002 -0400, you wrote:
Re-reading the info I have, I just realized that each cycle of the clock
run-in is, in fact, one bit width.
So what's the width ratio between clock run-in high-point (as square wave)
and a data bit? I'm assuming 8/1? A player pixel is 1/4 of a playfield
pixel and to do the CC you'd want to just double up the data bits into two
playfield bits per data bit, hence 8 player pixel widths per data bit.
I was counting on CC having convenient timing characteristics linked to the
colorburst frequency, colorclocks, etc.... It would have been a logical
design decision as it was with the 2600 itself. But maybe this wasn't the
case?
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