Re: [stella] FE, 3F, Bankswitching, and Data lines

Subject: Re: [stella] FE, 3F, Bankswitching, and Data lines
From: mickey_m@xxxxxxxxx
Date: Sun, 22 Dec 2002 04:35:35 +0000
I am using the Xilinx webpack software.  The normal simulation is exactly as 
you described, a logical, functional simulation.  The post fit simulation 
takes into account chip specific issues and part placement.
> What kind of simulator are you using? There are some simulators where you can 
> choose real simulation (considering delays - also know timing simluation) or 
> logical simulation (it considers only logical equations, without delays).
> 
> Max
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