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Subject: Re: [stella] FE, 3F, Bankswitching, and Data lines From: "Matthias Hartl" <maze@xxxxxxxxxxxxxx> Date: Mon, 23 Dec 2002 20:22:07 +0100 |
Hello, If anyone needs some help with VHDL I'd be glad to asisst. I just synthesized the arithmetic pipeline of a DLX RISC processor as lab course at my university. With kind regards, Matthias ---------------------------------------------------------------------------------------------- Archives (includes files) at http://www.biglist.com/lists/stella/archives/ Unsub & more at http://www.biglist.com/lists/stella/
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