Re: [stella] FE, 3F, Bankswitching, and Data lines

Subject: Re: [stella] FE, 3F, Bankswitching, and Data lines
From: Daniel Boris <dboris@xxxxxxxxxxx>
Date: Sat, 21 Dec 2002 15:16:08 -0500
If you check out you can find 6502 datasheets that have timing 
diagrams. According the the Rockwell datasheet, at 1Mhz you have 650ns 
to get the data valid, then you have to hold it valid for at least 


----- Original Message -----
From: Mickey Mouse <snafles@xxxxxxxxxxx>
Date: Tuesday, December 17, 2002 6:03 pm
Subject: Re: [stella] FE, 3F, Bankswitching, and Data lines

> When I was making mine, I put a frequency counter
> on A12.  I know its not the most accurate, but it
> registered around 1MHz.  Which was enough for me
> to figure out the the microcontroller I was using
> couldnt possibly get the job done.  I would
> recommend using the Xilix XC9500 CLPDs.  They are
> easy to use, the software is free.  I dont know
> Verilog or VHDL, I use the schematics editor.
> I had never used anything like a CLPD before this,
> and if I can figure it out, anyone can.
> Check out
> They have a nice tutorial and I ended up buying
> their board and programmer.
> Good Luck, its not too hard.
> PS  An early tip, long wires off VCS, very bad.
> >My last concern is timing.  How long do I have to get valid data on
> >the bus once the 2600 has set up the address lines?
> >
> >The FAQ lists the bus speed as 1.19 MHz.  Does that mean I have
> >less than 840 nS to get the data lines valid?
> >
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