Re: [stella] FE, 3F, Bankswitching, and Data lines

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Re: [stella] FE, 3F, Bankswitching, and Data lines

Subject: Re: [stella] FE, 3F, Bankswitching, and Data lines
From: Maximiliam Luppe <maxluppe@xxxxxxxxxxxx>
Date: Mon, 23 Dec 2002 15:08:30 -0200

Quoting mickey_m@xxxxxxxxx:

> I am using the Xilinx webpack software.  The normal simulation is exactly as
> 

I am using Altera MAX+plus II BASELINE and Quartus Web Edition. I got a delay 
line implementing a chain of LCELLs (see attached file) in MAX+plus II.

Max

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Current Thread
Re: [stella] FE, 3F, Bankswitching, and Data lines, (continued) Matthias Hartl - Mon, 23 Dec 2002 14:16:31 -0500 (EST) Mickey Mouse - Fri, 20 Dec 2002 10:29:31 -0500 (EST) Daniel Boris - Sat, 21 Dec 2002 19:39:38 -0500 (EST) mickey_m - Sat, 21 Dec 2002 23:36:07 -0500 (EST) Maximiliam Luppe - Fri, 27 Dec 2002 13:51:54 -0500 (EST) <=

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